1. Field of the Invention
The present invention relates to a system controller including a plurality of CPUs connected through a bus using a cross bar switch, and more specifically to a controller of a multi function peripheral with the view of controlling a scanning device, a printing device, a network interface, etc.
2. Related Background Art
(1) Conventionally, there has been a multiprocessor system in which a plurality of CPUs 2001, a memory controller, a DMAC, etc. are connected to a common bus 2126 as shown in FIG. 12.
(2) There has also been a system in which a plurality of CPUs are connected to the master ports of a plurality of concurrently connectable bus switches.
(3) Furthermore, there has been a suggested configuration in which a common bus is connected to one of the master ports of the bus switches.
However, there have been the following problems with the above-mentioned conventional technologies.
In the conventional technology (1) above, it is easy to perform coherency management of cache memory by bus snooping, to realize an atomic transaction, etc., but the master device connected to the common bus can be used only one at a time. Additionally, when there are a number of devices connected to a common bus, a high-performance operation is difficult due to a limit to an operation frequency, etc.
In the conventional technology (2) above, a high-performance operation can be realized by a possible concurrent connection and the reduction of a bus load, but a CPU cannot observe a bus transaction of another CPU, and it is hard to support the coherency management of cache memory, a load link, and a store conditional atomic transaction. To solve the problem, there is a method suggested in which one transaction of a CPU is transferred to another CPU before it is transmitted to a target slave, and cache coherence is maintained and an atomic transaction is realized through a snooping operation.
However, in this method, a writing operation is held until the completion of the snooping operation, thereby restricting the performance of the CPU. Furthermore, when a write buffer is implemented, and a first CPU is performing a writing operation, a second CPU cannot detect the writing operation until the first CPU completes it, and cannot break a link bit. Therefore, an atomic transaction cannot be guaranteed.
In the conventional technology (3) above, the above-mentioned problems can be solved, but when a first CPU connected to the common bus issues a transfer request to a low-speed device having a long access time, and a second CPU tries to access a high-speed device such as memory, etc., the access of the second CPU is held until the first CPU which issued the transfer request has completed its transfer, thereby restricting the improvement of the high performance by a plurality of CPUs.